Search results for "Nanocrystal memory"
showing 3 items of 3 documents
Memory effects in MOS capacitors with silicon quantum dots
2001
To form crystalline Si dots embedded in SiO2, we have deposited thin films of silicon-rich oxide (SRO) by plasma-enhanced chemical vapor deposition of SiH4 and O2. Then the materials have been annealed in N2 ambient at temperatures between 950°C and 1100°C. Under such processing, the supersaturation of Si in the amorphous SRO film produces the formation of crystalline Si dots embedded in SiO2. The narrow dot size distributions, analyzed by transmission electron microscopy, are characterized by average grain radii and standard deviations down to about 1 nm. The memory functions of such structures has been investigated in MOS capacitors with a SRO film sandwiched between two thin SiO2 layers …
Memory effects in MOS devices based on Si quantum dots
2003
Silicon quantum dots have been deposited on top of a 3-nm tunnel oxide by Low Pressure Chemical Vapour Deposition (LPCVD) and coated with a 7-nm Chemical Vapour Deposited (CVD) oxide. This stack was then incorporated in Metal-Oxide-Semiconductor structure and used as floating gate of a memory cell. The presence of 3 nm of tunnel oxides allows the injection of the charge by direct tunnel (DT) using low voltages for both program and erase operations. The charge stored in the quantum dots is able to produce a well-detectable flat band shift in the capacitors or, equivalently, a threshold voltage shift in the transistors. Furthermore, due to the presence of SiO 2 between the grains, the lateral…
Programming options for nanocrystal MOS memories
2003
Nanocrystal memories represent a promising candidate for the scaling of FLASH memories. In these devices, the charge is not stored in a continuous floating gate but in a discontinuous layer composed by numerous discrete silicon quantum dots well separated one from the other.The nanocrystals of radius of few nanometers are realized by chemical vapor deposition (CVD) of silicon on the tunnel oxide of 2.8 nm of thickness. These islands have been coated with a control oxide of 7 nm formed by CVD and incorporated in Metal-Oxide-Semiconductor structure. The devices are programmed and erased by tunnelling using low voltages and fast times. In addition, the programming can be easily achieved also b…